CY7B952-SC Datasheet Download

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CY7B952-SC
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Download Datasheet
Description:
[SSTTM SONET/SDH Serial Transceiver]
File Size:
135 K
Page:
9 Pages
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Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY7B952
fiber and some copper based systems use external threshold
detection circuitry to monitor the incoming data stream. The
CD input is a 100K PECL compatible signal that should be held
HIGH when the incoming data stream is valid. When CD is
pulled to a PECL LOW (<2.5V Max.), the LFI output will
transition LOW and the Receiver PLL will align itself with the
REFCLK×8 frequency and the recovered data outputs (RSER)
will remain LOW regardless of the signal level on the Receive
data-stream inputs (RIN).
In addition, the SST has a built-in transitions detector that also
checks the quality of the incoming data stream. The absence
of data transition can be caused by a broken transmission
media, a broken transmitter, or a problem with the transmit or
receive media coupling. The SST will detect a quiet link by
counting the number of bit times that have passed without a
data transition. A bit time is defined as the period of RCLK±.
When 512 bit times have passed without a data transition on
RIN±, LFI will transition LOW. The receiver will assume that
the serial data stream is invalid and, instead of allowing the
RCLK± frequency to wander in the absence of data, the PLL
will lock to the REFCLK*8 frequency. This will insure that
RCLK± is as close to the correct link operating frequency as
the REFCLK accuracy. LFI will be driven HIGH again and the
receiver will recover clock and data from the incoming data
stream when the transition detection circuitry determines that
at least 64 transitions have been detected within 512 bit-times.
The Transition Detector can be turned off by pulling the CD
input to a TTL LOW (<0.8V). When CD is pulled to a TTL LOW
the LFI will only be driven LOW if the incoming data stream
frequency is not within 1000 ppm of the REFCLK×8 frequency.
LFI LOW in this case will only indicate that the Receiver PLL
is Out of Lock (OOL). When this pin is left unconnected, an
internal pull-down resistor will pull this input to Ground.
Loop Back Testing
The TTL level LOOP pin is used to perform loop-back testing.
When LOOP is asserted (held LOW) the Transmitter serial
input (TSER±) is used by the Receiver PLL for clock and data
recovery. This allows in-system testing to be performed on the
entire device except for the differential Transmit drivers
(TOUT±) and the differential Receiver inputs (RIN±). For
example, an ATM controller can present ATM cells to the input
of the ATM cell processor and check to see that these same
cells are received. When the LOOP input is deasserted (held
HIGH) the Receive PLL is once again connected to the
Receiver serial inputs (RIN±).
The LOOP feature can also be used in applications where
clock and data recovery are to be performed from either of two
data streams. In these systems the LOOP pin is used to select
whether the TSER± or the RIN± inputs are used by the
Receive PLL for clock and data recovery.
SONET-compliant Testing
SONET jitter criteria for Bellcore-compliant are specified in
three areas: Jitter transfer, jitter tolerance and jitter generation.
Jitter transfer and jitter tolerance measurements were done
using sinusoidal jitter applied to the input signal at the
maximum amplitude of the jitter tolerance mask for each
specific jitter frequency as specified by the Bellcore
GR-253-Core Issue 2, Dec 1995 - SONET Common Generic
Criteria.
Power Down Modes
There are several power-down features on the SST. Any of the
differential output drivers can be powered down by either tying
both outputs to V
CC
or by simply leaving them unconnected
where internal pull-up resistors will force these outputs to V
CC
.
This will save approximately 4 mA per output pair in addition
to the associated output current. If the TOUT± or ROUT±
outputs are tied to V
CC
or left unconnected, the Transmit buffer
or Receive buffer path respectively will be turned off. If the
TCLK± outputs are tied to V
CC
or left unconnected, the entire
Transmit PLL will be powered down.
By leaving both the RCLK± and RSER± outputs unconnected
or tied to VCC, the entire Receive PLL is turned off. Even
though the Receive PLL may be turned off, the Link Fault
Indicator (LFI) will still reflect the state of the Carrier Detect
(CD) input. This feature can be used for aggressive power
management.
Applications
The SST can provide clock and data recovery as well as output
buffering for physical layer protocol engines such as those
used in WAN SONET/SDH and ATM applications. The
operating frequency of the 7B952 is centered around the
SONET/SDH STS-1 rate of 51.84 MHz and the SONET/SDH
STS-3/STM-1 rate of 155.52 MHz. This device can also be
used in data mover, Local Area Network (LAN) applications
that operate at these frequencies.
In an ATM system, the SST is used to recover clock and data
from an input SONET/SDH serial data stream for subsequent
chips to do serial to parallel conversion, SONET/SDH
overhead processing, ATM cell processing, and switching. On
the Transmit side, ATM cells coming out of a switching matrix
goes through ATM cell processing, SONET/SDH overhead
processing and parallel to serial conversion before passing to
the SST which buffers the data stream and drive the trans-
mission media.
In a more generic telecommunications system (Figure
1),
the
SST is used to provide clock and data recovery for a pure
SONET/SDH system such as a SONET/SDH switch. The SST
provides the recovered clock and data to a serial to parallel
converter and SONET/SDH Transport Overhead Processor
such as the PMC-Sierra PM5343 STXC. The parallel data is
then passed to a SONET/SDH Path Overhead Processor such
as the PMC-Sierra PM5344 SPTX.
Document #: 38-02018 Rev. *B
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