This line receiver port connects the receive differential serial input data stream to
the internal Receive PLL. This PLL will recover the embedded clock (RCLK±) and data (RSER±)
information for one of two data rates depending on the state of the MODE pin. These inputs can
receive very low amplitude signals and are compatible with all PECL signalling levels. If the RIN±
inputs are not being used, connect RIN+ to V
and RIN– to V
Passive Filter Capacitor Connection.
These pins are used to connect the external loop damping
capacitor and resistor for the internal clock and data recovery phase locked loop. A 301K
resistor and a non-polar 1
10% chip capacitor should be used in parallel for this connection.
Recovered Serial Data.
These ECL 100K outputs (+5V referenced) represent the recovered data
from the input data stream (RIN±). This recovered data is aligned with the recovered clock (RCLK±)
with a sampling window compatible with most data processing devices.
These ECL 100K outputs (+5V referenced) represent the recovered clock from
the input data stream (RIN±). This recovered clock is used to sample the recovered data (RSER±)
and has timing compatible with most data processing devices. If both the RSER± and the RCLK±
are tied to V
or left unconnected, the entire Receive PLL will be powered down.
This input controls the recovery function of the Receive PLL and can be driven by
the carrier detect output from optical modules or from external transition detection circuitry. When
this input is at an ECL HIGH, the input data stream (RIN±) is recovered normally by the Receive
PLL. When this input is at an ECL LOW, the Receive PLL no longer aligns to RIN±, but instead
aligns with the REFCLK×8 frequency. Also, the Link Fault Indicator (LFI) will transition LOW, and
the recovered data outputs (RSER) will remain LOW regardless of the signal level on the Receive
data-stream inputs (RIN). When the CD input is at a TTL LOW, the internal transitions detection
circuitry is disabled.
Link Fault Indicator.
This output indicates the status of the input data stream (RIN±). It is controlled
by three functions; the Carrier Detect (CD) input, the internal Transition Detector, and the Out of
Lock (OOL) detector. The Transition Detector determines if RIN± contains enough transitions to be
accurately recovered by the Receive PLL. The Out of Lock detector determines if RIN± is within the
frequency range of the Receive PLL. When CD is HIGH and RIN± has sufficient transitions and is
within the frequency range of the Receive PLL, the LFI output will be HIGH. If CD is at an ECL LOW
or RIN± does not contain sufficient transitions or RIN± is outside the frequency range of the Receive
PLL then the LFI output will be LOW. If CD is at a TTL LOW then the LFI output will only transition
LOW when the frequency of RIN± is outside the range of the Receive PLL.
Transmit Serial Data.
This line receiver port connects the transmit differential serial input data
stream to the TOUT transmit buffers. Depending on the state of the LOOP pin, this input port can
also be set up to supply the serial input data stream to the Receive PLL. These inputs can receive
very low amplitude signals and are compatible with all PECL signalling levels. If the TSER± inputs
are not being used, connect TSER+ to V
and TSER– to V
These ECL 100K outputs (+5V referenced) represent the buffered version of the
Transmit data stream (TSER±). This Transmit path is used to take weak input signals and rebuffer
them to drive low impedance copper media.
This input is the clock frequency reference for the clock and data recovery
Receive PLL. REFCLK is multiplied internally by eight and sets the approximate center frequency
for the internal Receive PLL to track the incoming bit stream. This input is also multiplied by eight
by the frequency multiplier Transmit PLL to produce the bit rate Transmit Clock (TCLK±). REFCLK
can be connected to either a differential PECL or single-ended TTL frequency source. When either
REFCLK+ or REFCLK– is at a TTL LOW, the opposite REFCLK signal becomes a TTL level input.
These ECL 100K outputs (+5V referenced) provide the bit rate frequency source
for external Transmit data processing devices. This output is synthesized by the Transmit PLL and
is derived by multiplying the REFCLK frequency by eight. When this output is turned off, the entire
Transmit PLL is powered down. All PECL outputs can be powered down by connecting both outputs
or leaving them both unconnected.
Loop Back Select.
This input is used to select the input data stream source that the Receive PLL
uses for clock and data recovery. When the LOOP input is HIGH, the Receive input data stream
(RIN±) is used for clock and data recovery. When LOOP is LOW, the Transmit input data stream
(TSER±) is used by the Receive PLL for clock and data recovery.
Document #: 38-02018 Rev. *B
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