CY7B933 HOTLink Receiver
REFCLK is the clock frequency reference for the clock/data synchronizing PLL.
REFCLK sets the approximate center frequency for the internal PLL to track the incoming bit stream.
REFCLK must be connected to a crystal-controlled time base that runs within the frequency limits of
the Tx/Rx pair, and the frequency must be the same as the transmitter CKW frequency (within
Decoder Mode Select.
The level on the MODE pin determines the decoding method to be used.
When wired to GND, MODE selects 8B/10B decoding. When wired to V
, registered shifter contents
bypass the decoder and are sent to Q
directly. When left floating (internal resistors hold the MODE
pin at V
/2) the internal bit clock generator is disabled and INB becomes the bit rate test clock to be
used for factory test. In typical applications, MODE is wired to V
Built-In Self-Test Enable.
When BISTEN is LOW the Receiver awaits a D0.0 (sent once per BIST
loop) character and begins a continuous test sequence that tests the functionality of the Transmitter,
the Receiver, and the link connecting them. In BIST mode the status of the test can be monitored with
RDY and RVS outputs. In normal use BISTEN is held HIGH or wired to V
. BISTEN has the same
timing as Q
Power for output drivers.
Power for internal circuitry.
time passes with the inputs disabled, the Encoder will output
a Special Character Comma K28.5 (or SYNC) that will
maintain link synchronization. SVS input forces the trans-
mission of a specified Violation symbol to allow the user to
check error handling system logic in the controller or for propri-
The 8B/10B coding function of the Encoder can be bypassed
for systems that include an external coder or scrambler
function as part of the controller. This bypass is controlled by
setting the MODE select pin HIGH. When in bypass mode, D
(note that bit order is specified in the Fibre Channel 8B/10B
code) become the ten inputs to the Shifter, with D
first bit to be shifted out.
The Shifter accepts parallel data from the Encoder once each
byte time and shifts it to the serial interface output buffers using
a PLL multiplied bit clock that runs at ten (10) times the byte
clock rate. Timing for the parallel transfer is controlled by the
counter included in the Clock Generator and is not affected by
signal levels or timing at the input pins.
OutA, OutB, OutC
The serial interface PECL output buffers (ECL100K refer-
enced to +5V) are the drivers for the serial media. They are all
connected to the Shifter and contain the same serial data. Two
of the output pairs (OUTA± and OUTB±) are controllable by the
FOTO input and can be disabled by the system controller to
force a logical zero (i.e., “light off”) at the outputs. The third
output pair (OUTC±) is not affected by FOTO and will supply
a continuous data stream suitable for loop-back testing of the
OUTA± and OUTB± will respond to FOTO input changes
within a few bit times. However, since FOTO is not synchro-
nized with the transmitter data stream, the outputs will be
forced off or turned on at arbitrary points in a transmitted byte.
This function is intended to augment an external laser safety
controller and as an aid for Receiver PLL testing.
CY7B923 HOTLink Transmitter Block Diagram
The Input register holds the data to be processed by the
HOTLink transmitter and allows the input timing to be made
consistent with standard FIFOs. The Input register is clocked
by CKW and loaded with information on the D
, SC/D, and
SVS pins. Two enable inputs (ENA and ENN) allow the user
to choose when data is loaded in the register. Asserting ENA
(Enable, active LOW) causes the inputs to be loaded in the
register on the rising edge of CKW. If ENN (Enable Next, active
LOW) is asserted when CKW rises, the data present on the
inputs on the next rising edge of CKW will be loaded into the
Input register. If neither ENA nor ENN are asserted LOW on
the rising edge of CKW, then a SYNC (K28.5) character is
sent. These two inputs allow proper timing and function for
compatibility with either asynchronous FIFOs or clocked
FIFOs without external logic, as shown in
In BIST mode, the Input register becomes the signature
pattern generator by logically converting the parallel Input
register into a Linear Feedback Shift Register (LFSR). When
enabled, this LFSR will generate a 511-byte sequence that
includes all Data and Special Character codes, including the
explicit violation symbols. This pattern provides a predictable
but pseudo-random sequence that can be matched to an
identical LFSR in the Receiver.
The Encoder transforms the input data held by the Input
register into a form more suitable for transmission on a serial
interface link. The code used is specified by ANSI X3.230
(Fibre Channel) and the IBM ESCON channel (code tables are
at the end of this data sheet). The eight D
data inputs are
converted to either a Data symbol or a Special Character,
depending upon the state of the SC/D input. If SC/D is HIGH,
the data inputs represent a control code and are encoded
using the Special Character code table. If SC/D is LOW, the
data inputs are converted using the Data code table. If a byte
Document #: 38-02017 Rev. *E
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