CY6264-70SNC Datasheet Download

Part No.:
CY6264-70SNC
Download:
Download Datasheet
Description:
[8K x 8 Static RAM]
File Size:
256 K
Page:
9 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY6264-70SNC Datasheet Page:2CY6264-70SNC Datasheet Page:3CY6264-70SNC Datasheet Page:4CY6264-70SNC Datasheet Page:5CY6264-70SNC Datasheet Page:6CY6264-70SNC Datasheet Page:7CY6264-70SNC Datasheet Page:8CY6264-70SNC Datasheet Page:9 
CY6264
8K x 8 Static RAM
Features
• Temperature Ranges
— Commercial: 0°C to 70°C
— Industrial: –40°C to 85°C
— Automotive-A: –40°C to 85°C
• High Speed
55 ns
• CMOS for optimum speed/power
• Easy memory expansion with CE
1
, CE
2
and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 28-lead SNC
package
Functional Description
The CY6264 is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE
1
), an active
HIGH chip enable (CE
2
), and active LOW output enable (OE)
and three-state drivers. Both devices have an automatic
power-down feature (CE
1
), reducing the power consumption
by over 70% when deselected. The CY6264 is packaged in a
450-mil (300-mil body) SOIC.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE
1
and WE
inputs are both LOW and CE
2
is HIGH, data on the eight data
input/output pins (I/O
0
through I/O
7
) is written into the memory
location addressed by the address present on the address
pins (A
0
through A
12
). Reading the device is accomplished by
selecting the device and enabling the outputs, CE
1
and OE
active LOW, CE
2
active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins is present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH. A die coat is used to ensure alpha immunity.
Logic Block Diagram
Pin Configuration
SOIC
Top View
NC
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
CE
2
A
3
A
2
A
1
OE
A
0
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
I/O
1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
8K x 8
ARRAY
CE
1
CE
2
WE
OE
COLUMN DECODER
POWER
DOWN
I/O
7
A
10
A
11
A
0
A
9
A
12
Cypress Semiconductor Corporation
Document #: 001-02367 Rev. *A
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 8, 2006