CY62256NLL-70SNXC Datasheet Download

Part No.:
CY62256NLL-70SNXC
Download:
Download Datasheet
Description:
[256K (32K × 8) Static RAM]
File Size:
577 K
Page:
14 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY62256N
256K (32K × 8) Static RAM
256K (32K × 8) Static RAM
Features
Functional Description
The CY62256N
is a high performance CMOS static RAM
organized as 32K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE) and active LOW
output enable (OE) and tristate drivers. This device has an
automatic power down feature, reducing the power consumption
by 99.9 percent when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE and WE
inputs are both LOW, data on the eight data input/output pins
(I/O
0
through I/O
7
) is written into the memory location addressed
by the address present on the address pins (A
0
through A
14
).
Reading the device is accomplished by selecting the device and
enabling the outputs, CE and OE active LOW, while WE remains
inactive or HIGH. Under these conditions, the contents of the
location addressed by the information on address pins are
present on the eight data input/output pins.
The input/output pins remain in a high impedance state unless
the chip is selected, outputs are enabled, and write enable (WE)
is HIGH.
Temperature Ranges
Commercial: 0 °C to +70 °C
Industrial: –40 °C to +85 °C
Automotive-A: –40 °C to +85 °C
Automotive-E: –40 °C to +125 °C
High Speed: 55 ns
Voltage Range: 4.5 V to 5.5 V Operation
Low Active Power
275 mW (max)
Low Standby Power (LL version)
82.5
W
(max)
Easy Memory Expansion with CE and OE Features
TTL-Compatible Inputs and Outputs
Automatic Power Down when Deselected
CMOS for Optimum Speed and Power
Available in Pb-free and non Pb-free 28-pin (600-mil) PDIP,
28-pin (300-mil) Narrow SOIC, 28-pin TSOP-I, and 28-pin
Reverse TSOP-I Packages
Logic Block Diagram
INPUTBUFFER
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
CE
WE
OE
A
14
A
13
A
12
A
11
A
1
A
0
ROW DECODER
I/O
0
I/O
1
SENSE AMPS
I/O
2
I/O
3
I/O
4
I/O
5
32K x 8
Y
ARRA
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
Note
1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on
http://www.cypress.com.
Cypress Semiconductor Corporation
Document Number: 001-06511 Rev. *D
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised January 4, 2011