CY62148ELL-55SXI Datasheet Download

Part No.:
CY62148ELL-55SXI
Download:
Download Datasheet
Description:
[4-Mbit (512 K × 8) Static RAM]
File Size:
407 K
Page:
14 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY62148E MoBL
®
4-Mbit (512 K × 8) Static RAM
4-Mbit (512 K × 8) Static RAM
Features
Functional Description
The CY62148E is a high performance CMOS static RAM
organized as 512 K words by 8-bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device into standby mode reduces power consumption by more
than 99% when deselected (CE HIGH). The eight input and
output pins (I/O
0
through I/O
7
) are placed in a high impedance
state when the device is deselected (CE HIGH), Outputs are
disabled (OE HIGH), or during an active Write operation (CE
LOW and WE LOW)
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O
0
through I/O
7
)
is then written into the location specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
For best practice recommendations, refer to the Cypress
application note
Very high speed: 45 ns
Voltage range: 4.5 V to 5.5 V
Pin compatible with CY62148B
Ultra low standby power
Typical standby current: 1 µA
Maximum standby current: 7 µA (Industrial)
Ultra low active power
Typical active current: 2.0 mA at f = 1 MHz
Easy memory expansion with CE, and OE features
Automatic power-down when deselected
Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC)
packages
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
CE
WE
OE
INPUT BUFFER
ROW DECODER
I/O
IO0
0
I/O
IO1
1
SENSE AMPS
I/O
IO2
2
I/O
IO3
3
I/O
IO4
4
I/O
IO5
5
I/O
IO6
6
I/O
512K x 8
ARRAY
COLUMN DECODER
POWER
DOWN
IO7
7
A13
A15
A16
A17
Note
1. SOIC package is available only in 55 ns speed bin.
A14
A18
Cypress Semiconductor Corporation
Document #: 38-05442 Rev. *H
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 23, 2010