CY62157EV30LL-45ZSXI Datasheet Download

Part No.:
CY62157EV30LL-45ZSXI
Download:
Download Datasheet
Description:
[8-Mbit (512K x 16) Static RAM]
File Size:
627 K
Page:
14 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY62157EV30 MoBL
®
8-Mbit (512K x 16) Static RAM
Features
• TSOP I package configurable as 512K x 16 or as 1M x 8
SRAM
• High speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin compatible with CY62157DV30
• Ultra low standby power
— Typical Standby current: 2
µA
— Maximum Standby current: 8
µA
(Industrial)
• Ultra low active power
— Typical active current: 1.8 mA @ f = 1 MHz
Easy memory expansion with CE
1
, CE
2
, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Available in both Pb-free and non Pb-free 48-ball VFBGA,
Pb-free 44-pin TSOP II and 48-pin TSOP I packages
reduces power consumption when addresses are not toggling.
Place the device into standby mode when deselected (CE
1
HIGH or CE
2
LOW or both BHE and BLE are HIGH). The input
or output pins (IO
0
through IO
15
) are placed in a high
impedance state when:
• Deselected (CE
1
HIGH or CE
2
LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH)
• Write operation is active (CE
1
LOW, CE
2
HIGH and WE
LOW)
To write to the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO
0
through IO
7
) is
written into the location specified on the address pins (A
0
through A
18
). If Byte High Enable (BHE) is LOW, then data
from IO pins (IO
8
through IO
15
) is written into the location
specified on the address pins (A
0
through A
18
).
To read from the device, take Chip Enable (CE
1
LOW and CE
2
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then
data from the memory location specified by the address pins
appear on IO
0
to IO
7
. If Byte High Enable (BHE) is LOW, then
data from memory appears on IO
8
to IO
15
. See the
for a complete description of read and write
modes.
Functional Description
The CY62157EV30 is a high performance CMOS static RAM
organized as 512K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
Logic Block Diagram
DATA IN DRIVERS
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
ROW DECODER
512K × 16 / 1M x 8
RAM Array
SENSE AMPS
IO
0
–IO
7
IO
8
–IO
15
COLUMN DECODER
CE
2
BYTE
BHE
WE
OE
BLE
Notes
1. For best practice recommendations, please refer to the Cypress application note
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
Power Down
Circuit
CE
1
BHE
BLE
CE
2
CE
1
Cypress Semiconductor Corporation
Document #: 38-05445 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised May 07, 2007