CY62148ELL-55SXI Datasheet Download

Part No.:
CY62148ELL-55SXI
Download:
Download Datasheet
Description:
[4-Mbit (512K x 8) Static RAM]
File Size:
942 K
Page:
10 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY62148E MoBL
®
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................ –65°C to + 150°C
Ambient Temperature with
Power Applied............................................ –55°C to + 125°C
Supply Voltage to Ground
Potential .................................–0.5V to 6.0V (V
CCmax
+ 0.5V)
DC Voltage Applied to Outputs
in High-Z State
................–0.5V to 6.0V (V
CCmax
+ 0.5V)
DC Input Voltage
............ –0.5V to 6.0V (V
CCmax
+ 0.5V)
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current ......................................................>200mA
Operating Range
Device
CY62148E
Range
Ind’l/Auto-A
Ambient
Temperature
–40°C to +85°C
V
CC
4.5V to 5.5V
Electrical Characteristics
(Over the Operating Range)
Parameter
V
OH
V
OL
V
IH
V
IL
Description
Output HIGH
Voltage
Test Conditions
I
OH
= –1 mA
45 ns
Min Typ
2.4
0.4
2.2
–0.5
V
CC
+ 0.5 2.2
0.8
–0.5
–1
–1
15
2
1
+1
+1
20
2.5
7
–1
–1
15
2
1
0.6
+1
+1
20
2.5
7
µA
µA
µA
mA
Max
2.4
0.4
V
CC
+ 0.5
55 ns
Min Typ
Max
Unit
V
V
V
V
Output LOW Voltage I
OL
= 2.1 mA
Input HIGH Voltage V
CC
= 4.5V to 5.5V
Input LOW voltage
V
CC
= 4.5V to 5.5V For TSOPII
package
For SOIC
package
I
IX
I
OZ
I
CC
I
SB2 [9]
Input Leakage
Current
Output Leakage
Current
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
max
= 1/t
RC
f = 1 MHz
V
CC
= V
CC(max)
I
OUT
= 0 mA
CMOS levels
Automatic CE Power CE > V
CC
– 0.2V
down Current —
V
IN
> V
CC
– 0.2V or V
IN
< 0.2V,
CMOS Inputs
f = 0, V
CC
= V
CC(max)
Capacitance
(For All Packages)
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= V
CC(typ)
Max
10
10
Unit
pF
pF
Notes
5. V
IL(min)
= –2.0V for pulse durations less than 20 ns for I < 30 mA.
6. V
IH(max)
= V
CC
+0.75V for pulse durations less than 20 ns.
7. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to V
CC
(min) and 200 µs wait time after V
CC
stabilization.
8. Under DC conditions the device meets a V
IL
of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.6V. This
is applicable to SOIC package only. Refer to AN13470 for details.
9. Only chip enable (CE) must be HIGH at CMOS level to meet the I
SB2
spec. Other inputs can be left floating.
10. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05442 Rev. *F
Page 3 of 10