CY62147CV18LL-70BAI Datasheet Download

Part No.:
CY62147CV18LL-70BAI
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Download Datasheet
Description:
[256K x 16 Static RAM]
File Size:
275 K
Page:
12 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY62147CV18 MoBL2™
Switching Characteristics
Over the Operating Range
[8]
55 ns
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
BW
t
SD
t
HD
t
HZWE
t
LZWE
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[9]
OE HIGH to High Z
[9, 10]
CE LOW to Low Z
[9]
CE HIGH to High Z
[9, 10]
CE LOW to Power-Up
CE HIGH to Power-Down
BLE/BHE LOW to Data Valid
BLE/BHE LOW to Low Z
[9]
BLE/BHE HIGH to High Z
[9, 10]
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
BLE/BHE LOW to Write End
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
[9, 10]
WE HIGH to Low Z
[9]
5
55
40
40
0
0
40
40
25
0
15
10
5
20
70
60
60
0
0
50
60
30
0
25
0
55
55
5
25
5
20
0
70
70
5
20
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
70 ns
Max.
Unit
WRITE CYCLE
[11]
Notes:
8. Test conditions assume signal transition time of 3ns or less, timing reference levels of V
CC(typ)
/2, input pulse levels of 0 to V
CC(typ)
, and output loading of the
specified I
OL
/I
OH
and 30-pF load capacitance.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high impedance state.
11. The internal write time of the memory is defined by the overlap of WE, CE = V
IL
, BHE and/or BLE =V
IL
. All signals must be ACTIVE to initiate a write and
any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that
terminates the write
Document #: 38-05011 Rev. *B
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