CY62128LL-70SC Datasheet Download

Part No.:
CY62128LL-70SC
Download:
Download Datasheet
Description:
[128K x 8 Static RAM]
File Size:
254 K
Page:
8 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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1CY 621 28
fax id: 1072
PRELIMINARY
CY62128
128K x 8 Static RAM
Features
• 4.5V
5.5V operation
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 330 mW (max.) (60 mA)
• Low standby power (70 ns, LL version)
— 110
µW
(max.) (20
µA)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE
1
, CE
2
, and OE options
feature that reduces power consumption by more than 75%
when deselected.
Writing to the device is accomplished by taking chip enable
one (CE
1
) and write enable (WE) inputs LOW and chip enable
two (CE
2
) input HIGH. Data on the eight I/O pins (I/O
0
through
I/O
7
) is then written into the location specified on the address
pins (A
0
through A
16
).
Reading from the device is accomplished by taking chip en-
able one (CE
1
) and output enable (OE) LOW while forcing
write enable (WE) and chip enable two (CE
2
) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE
1
LOW, CE
2
HIGH, and WE LOW).
The CY62128 is available in a standard 400-mil-wide SOJ,
525-mil wide (450-mil-wide body width) SOIC and 32-pin
TSOP type I.
Functional Description
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE
1
), an active HIGH
chip enable (CE
2
), an active LOW output enable (OE), and
three-state drivers. This device has an automatic power-down
Logic Block Diagram
Pin Configurations
Top View
SOJ / SOIC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
I/O
1
I/O
2
512 x 256 x 8
ARRAY
I/O
3
I/O
4
I/O
5
POWER
DOWN
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
NC
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CE
1
CE
2
WE
OE
COLUMN
DECODER
I/O
6
I/O
7
62128-1
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
62128-2
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
Cypress Semiconductor Corporation
3901 North First Street
San Jose
• CA 95134 •
408-943-2600
July 1996 - Revised November 1996