CY62128VLL-70ZAI Datasheet Download

Part No.:
CY62128VLL-70ZAI
Download:
Download Datasheet
Description:
[128K x 8 Static RAM]
File Size:
339 K
Page:
12 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY62128V Family
Data Retention Current Graph
(for “L” version only)
DATA RETENTIO N
CURRENT
vs. SUPPLY VOLTAGE
80
SUPPLY CURRENT
(µA)
70
60
50
40
30
20
10
0
2.6
1.6
3.6
T
A
=25°C
SUPPLY VOLTAGE (V)
Switching Characteristics
Over the Operating Range
62128V-55
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
5.
6.
7.
8.
9.
62128V-70
Min.
70
Max.
62128V25-100
Min.
100
Max.
62128V18-200
Min.
200
Max.
Unit
ns
200
10
200
125
10
75
10
75
0
200
200
190
190
0
0
125
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
15
ns
ns
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE LOW to High Z
WE HIGH to Low Z
Min.
55
Max.
55
5
55
20
10
20
10
20
0
55
55
45
45
0
0
45
25
0
20
5
5
70
60
60
0
0
55
30
0
0
10
10
10
70
10
70
35
10
25
10
25
0
70
100
100
100
0
0
90
60
0
25
10
100
100
75
50
50
100
50
Test conditions assume signal transition time of 5 ns or less timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 100-pF load capacitance.
At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
t
HZOE
, t
HZCE
, and t
HZWE
are specified with C
L
= 5 pF as in part (b) of AC Test Loads. Transition is measured ±200 mV from steady-state voltage.
The internal write time of the memory is defined by the overlap of CE
1
LOW, CE
2
HIGH, and WE LOW. CE
1
and WE signals must be LOW and CE
2
HIGH to initiate a
write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
5