CY28346ZC Datasheet Download

Part No.:
CY28346ZC
Download:
Download Datasheet
Description:
[Clock Synthesizer with Differential CPU Outputs]
File Size:
274 K
Page:
20 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY28346
Clock Synthesizer with Differential CPU Outputs
Features
• Compliant with Intel
®
CK 408 Mobile Clock Synthesizer
specifications
• 3.3V power supply
• Three differential CPU clocks
• Ten copies of PCI clocks
Table 1. Frequency Table
[1]
S2
1
1
1
1
0
0
0
0
M
M
S1
0
0
1
1
0
0
1
1
0
0
S0
0
1
0
1
0
1
0
1
0
1
CPU (0:2)
66M
100M
200M
133M
66M
100M
200M
133M
Hi-Z
TCLK/2
3V66
66M
66M
66M
66M
66M
66M
66M
66M
Hi-Z
TCLK/4
66BUFF(0:2)/
3V66(0:4)
66IN
66IN
66IN
66IN
66M
66M
66M
66M
Hi-Z
TCLK/4
66IN/3V66–5
66-MHz clock input
66-MHz clock input
66-MHz clock input
66-MHZ clock input
66M
66M
66M
66M
Hi-Z
TCLK/4
PCI_FPCI
66IN/2
66IN/2
66IN/2
66IN/2
33 M
33 M
33 M
33 M
Hi-Z
TCLK/8
REF
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
14.318M
Hi-Z
TCLK
USB/
DOT
48M
48M
48M
48M
48M
48M
48M
48M
Hi-Z
TCLK/2
• 5/6 copies of 3V66 clocks
• SMBus support with read-back capabilities
• Spread Spectrum electromagnetic interference (EMI)
reduction
• Dial-a-Frequency™ features
• Dial-a-dB™ features
• 56-pin TSSOP and SSOP packages
Block Diagram
XIN
XOUT
PLL1
CPU_STP#
IREF
VSSIREF
S(0:2)
MULT0
VTT_PG#
PCI_STP#
PLL2
WD
Logic
I2C
Logic
Power
Up Logic
/2
Pin Configuration
REF
CPUT(0:2)
CPUC(0:2)
VDD
XIN
XOUT
VSS
PCIF0
PCIF1
PCIF2
VDD
VSS
PCI0
PCI1
PCI2
PCI3
VDD
VSS
PCI4
PCI5
PCI6
VDD
VSS
66B0/3V66_2
66B1/3V66_3
66B2/3V66_4
66IN/3V66_5
PD#
VDDA
VSSA
VTT_PG#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF
S1
S0
CPU_STP#
CPUT0
CPUC0
VDD
CPUT1
CPUC1
VSS
VDD
CPUT2
CPUC2
MULT0
IREF
VSSIREF
S2
48MUSB
48MDOT
VDD
VSS
3V66_1/VCH
PCI_STP#
3V66_0
VDD
VSS
SCLK
SDATA
3V66_0
3V66_1/VCH
PCI(0:6)
PCI_F(0:2)
48M USB
48M DOT
CY28346
PD#
SDATA
SCLK
VDDA
66B[0:2]/3V66[2:4]
66IN/3V66-5
Note:
1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a
0 state will be latched into the device’s internal state register.
Cypress Semiconductor Corporation
Document #: 38-07331 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised March 11, 2005