CY28323PVC Datasheet Download

Part No.:
CY28323PVC
Download:
Download Datasheet
Description:
[FTG for Intel㈢ Pentium㈢ 4 CPU and Chipsets]
File Size:
175 K
Page:
22 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY28323PVC Datasheet Page:5CY28323PVC Datasheet Page:6CY28323PVC Datasheet Page:7CY28323PVC Datasheet Page:8CY28323PVC Datasheet Page:10CY28323PVC Datasheet Page:11CY28323PVC Datasheet Page:12CY28323PVC Datasheet Page:13 
PRELIMINARY
Data Byte 8
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Pin#
--
--
--
--
--
--
--
Reserved
Reserved
WD_TIMER4
WD_TIMER3
WD_TIMER2
WD_TIMER1
WD_TIMER0
Name
Reserved
Reserved
Pin Description
CY28323
Power On
Default
0
0
1
1
1
1
1
These bits store the time-out value of the WATCHDOG
timer. The scale of the timer is determine by the prescaler.
The timer can support a value of 150 ms to 4.8 sec when
the prescaler is set to 150 ms. If the prescaler is set to
2.5 sec, it can support a value from 2.5 sec to 80 sec.
When the Watchdog Timer reaches “0,” it will set the
WD_TO_STATUS bit and generate Reset if RST_EN_WD
is enabled.
0 = 150 ms
1 = 2.5 sec
Bit 0
--
WD_PRE_SCALER
0
Data Byte 9
Bit
Bit 7
Pin#
--
Name
48MHz_DRV
Pin Description
48-MHz & 24_48-MHz clock output drive strength
0 = Normal
1 = High Drive
(Recommend to set to high drive if this output is being
used to drive both USB and SIO devices in Intel®
Brookdale - G platforms)
PCI clock output drive strength
0 = Normal
1 = High Drive
3V66 clock output drive strength
0 = Normal
1 = High Drive
This bit will enable the generation of a Reset pulse when
a Watchdog Timer time-out occurs.
0 = Disabled
1 = Enabled
This bit will enable the generation of a Reset pulse after a
frequency change occurs.
0 = Disabled
1 = Enabled
Watchdog Timer Time-out Status bit
0 = No time-out occurs (Read); Ignore (Write)
1 = time-out occurred (Read); Clear WD_TO_STATUS
(Write)
0 = Stop and reload Watchdog Timer
1 = Enable Watchdog Timer. It will start counting down
after a frequency change occurs.
Note: CY28323 will generate system reset, reload a recov-
ery frequency, and lock itself into a recovery frequency
mode after a Watchdog timer time-out occurs. Under re-
covery frequency mode, CY28323 will not respond to any
attempt to change output frequency via the SMBus control
bytes. System software can unlock CY28323 from its re-
covery frequency mode by clearing the WD_EN bit.
Reserved
Power On
Default
0
Bit 6
--
PCI_DRV
0
Bit 5
--
3V66_DRV
0
Bit 4
--
RST_EN_WD
0
Bit 3
--
RST_EN_FC
0
Bit 2
--
WD_TO_STATUS
0
Bit 1
--
WD_EN
0
Bit 0
--
Reserved
0
Page 9 of 22
Document #: 38-07004 Rev. *B