CY2308SI-1H Datasheet Download

Part No.:
CY2308SI-1H
Download:
Download Datasheet
Description:
[3.3V Zero Delay Buffer]
File Size:
367 K
Page:
15 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
 CY2308SI-1H Datasheet Page:3CY2308SI-1H Datasheet Page:4CY2308SI-1H Datasheet Page:5CY2308SI-1H Datasheet Page:6CY2308SI-1H Datasheet Page:8CY2308SI-1H Datasheet Page:9CY2308SI-1H Datasheet Page:10CY2308SI-1H Datasheet Page:11 
CY2308
Switching Characteristics for Industrial Temperature Devices
Parameter
t
1
t
1
t
1
Name
Output Frequency
Output Frequency
Output Frequency
Duty
= t
2
÷
t
1
(–1, –2, –3, –4, –1H, –5H)
Cycle
Duty Cycle
= t
2
÷
t
1
(–1, –2, –3, –4, –1H, –5H)
t
3
t
3
t
3
t
4
t
4
t
4
t
5
Rise Time
(–1, –2, –3, –4)
Rise Time
(–1, –2, –3, –4)
Rise Time
(–1H, –5H)
Fall Time
(–1, –2, –3, –4)
Fall Time
(–1, –2, –3, –4)
Fall Time
(–1H, –5H)
Test Conditions
30 pF load, All devices
20 pF load, –1H, –5H devices
15 pF load, –1, –2, –3, –4 devices
Measured at 1.4V, F
OUT
= 66.66 MHz
30 pF load
Measured at 1.4V, F
OUT
<50.0 MHz
15 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
30 pF load
Measured between 0.8V and 2.0V,
15 pF load
Measured between 0.8V and 2.0V,
30 pF load
Min
10
10
10
40.0
45.0
1
Typ
50.0
50.0
0
0
75
Max
100
133.3
133.3
60.0
55.0
2.50
1.50
1.50
2.50
1.50
1.25
200
200
200
400
±250
700
200
200
100
400
400
1.0
Unit
MHz
MHz
MHz
%
%
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
V/ns
ps
ps
ps
ps
ps
ms
Output to Output Skew on
All outputs equally loaded
same Bank (–1, –2, –3, –4)
Output to Output Skew
(–1H, –5H)
Output Bank A to Output
Bank B Skew (–1, –4, –5H)
Output Bank A to Output
Bank B Skew (–2, –3)
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of
devices
Measured between 0.8V and 2.0V on –1H,
–5H device using Test Circuit 2
Measured at 66.67 MHz, loaded outputs,
15 pF load
Measured at 66.67 MHz, loaded outputs,
30 pF load
Measured at 133.3 MHz, loaded outputs,
15 pF load
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to
FBK Rising Edge
Device to Device Skew
Output Slew Rate
Cycle to Cycle Jitter
(–1, –1H, –4, –5H)
t
J
Cycle to Cycle Jitter
(–2, –3)
Measured at 66.67 MHz, loaded outputs
30 pF load
Measured at 66.67 MHz, loaded outputs
15 pF load
t
LOCK
PLL Lock Time
Stable power supply, valid clocks
presented on REF and FBK pins
Document Number: 38-07146 Rev. *E
Page 7 of 15