CY2308SI-1H Datasheet Download

Part No.:
CY2308SI-1H
Download:
Download Datasheet
Description:
[3.3V Zero Delay Buffer]
File Size:
367 K
Page:
15 Pages
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Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY2308
3.3V Zero Delay Buffer
Features
Zero input-output propagation delay, adjustable by
capacitive load on FBK input
Multiple configurations, see
Multiple low skew outputs
Two banks of four outputs, three-stateable by two select
inputs
10 MHz to 133 MHz operating range
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
Space saving 16-pin 150 mil SOIC package or 16-pin TSSOP
3.3V operation
Industrial Temperature available
required, Bank B is three-stated. The input clock is directly
applied to the output for chip and system testing purposes by
the select inputs.
The CY2308 PLL enters a power down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than
50
μA
of current draw. The PLL shuts down in two additional
cases as shown in the table
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as
shown in the table
frequencies equal the reference if there is no counter in the
feedback path. The CY2308–1H is the high drive version of the
–1 and rise and fall times on this device are much faster.
The CY2308–2 enables the user to obtain 2X and 1X
frequencies on each output bank. The exact configuration and
output frequencies depend on the output that drives the
feedback pin. The CY2308–3 enables the user to obtain 4X
and 2X frequencies on the outputs.
The CY2308–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308–5H is a high drive version with REF/2 on both
banks.
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin. The PLL feedback is driven into the
FBK pin and obtained from one of the outputs. The
input-to-output skew is less than 350 ps and output-to-output
skew is less than 200 ps.
The CY2308 has two banks of four outputs each that is
controlled by the Select inputs as shown in the table
Logic Block Diagram
/2
REF
PLL
MUX
FBK
CLKA1
CLKA2
CLKA3
CLKA4
/2
Extra Divider (–3, –4)
Extra Divider (–5H)
S2
S1
Select Input
Decoding
/2
CLKB1
CLKB2
CLKB3
Extra Divider (–2, –3)
CLKB4
Cypress Semiconductor Corporation
Document Number: 38-07146 Rev. *E
198 Champion Court
San Jose
,
CA 95134-1709
408-943-2600
Revised August 03, 2007