3.3V Zero Delay Buffer
• Zero input-output propagation delay, adjustable by
capacitive load on FBK input
• Multiple configurations – see “Available Configura-
• Multiple low-skew outputs
— Output-output skew less than 200 ps
— Device-device skew less than 500 ps
• 10-MHz to 133-MHz operating range
• Low jitter, less than 200 ps cycle-cycle
• Space-saving 8-pin 150-mil SOIC package
• 3.3V operation
• Industrial temperature available
The part has an on-chip phase-locked loop (PLL) that locks to
an input clock presented on the REF pin. The PLL feedback is
required to be driven into the FBK pin, and can be obtained
from one of the outputs. The input-to-output skew is
guaranteed to be less than 250 ps, and output-to-output skew
is guaranteed to be less than 200 ps.
The CY2304 has two banks of two outputs each.
The CY2304 PLL enters a power-down state when there are
no rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off, resulting in less than
of current draw.
Multiple CY2304 devices can accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is guaranteed to be less than 500 ps.
The CY2304 is available in two different configurations, as
shown in the “Available Configurations” table. The CY2304–1
is the base part, where the output frequencies equal the
reference if there is no counter in the feedback path.
The CY2304–2 allows the user to obtain Ref and 1/2x or 2x
frequencies on each output bank. The exact configuration and
output frequencies depends on which output drives the
The CY2304 is a 3.3V zero delay buffer designed to distribute
high-speed clocks in PC, workstation, datacom, telecom, and
other high-performance applications.
Logic Block Diagram
Extra Divider (-2)
Bank A or B
Bank A Frequency Bank B Frequency
2 × Reference
Cypress Semiconductor Corporation
Document #: 38-07247 Rev. *C
3901 North First Street
CA 95134 • 408-943-2600
Revised December 7, 2002