CY2292F Datasheet Download

Part No.:
CY2292F
Download:
Download Datasheet
Description:
[Three-PLL General-Purpose EPROM Programmable Clock Generator]
File Size:
191 K
Page:
11 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY2292
Three-PLL General-Purpose
EPROM Programmable Clock Generator
Features
• Three integrated phase-locked loops
• EPROM programmability
• Factory-programmable (CY2292) or field-program-
mable (CY2292F) device options
• Low-skew, low-jitter, high-accuracy outputs
• Power-management options (Shutdown, OE, Suspend)
• Frequency select option
• Smooth slewing on CPUCLK
• Configurable 3.3V or 5V operation
• 16-pin SOIC Package (TSSOP: F only)
Benefits
• Generates up to three custom frequencies from
external sources
• Easy customization and fast turnaround
• Programming support available for all opportunities
• Meets critical industry standard timing requirements
• Supports low-power applications
• Eight user-selectable frequencies on CPU PLL
• Allows downstream PLLs to stay locked on CPUCLK
output
• Enables application compatibility
• Industry-standard packaging saves on board space
Selector Guide
Part Number
CY2292
CY2292I
CY2292F
CY2292FI
CY2292FZ
Outputs
6
6
6
6
6
Input Frequency Range
Output Frequency Range
Specifics
Factory Programmable
Commercial Temperature
Factory Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
Field Programmable
Industrial Temperature
Field Programmable
Commercial Temperature
10 MHz–25 MHz (external crystal) 76.923 kHz–100 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–80 MHz (3.3V)
10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V)
10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V)
10 MHz–25 MHz (external crystal) 76.923 kHz–80 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–60.0 MHz (3.3V)
10 MHz–25 MHz (external crystal) 76.923 kHz–90 MHz (5V)
1 MHz–30 MHz (reference clock) 76.923 kHz–66.6 MHz (3.3V)
Logic Block Diagram
XTALIN
XTALOUT
S0
S1
S2/SUSPEND
.
OSC.
CPLL
(8 BIT)
/1,2,4
XBUF
CPUCLK
CLKA
UPLL
(10 BIT)
/1,2,4,8
/1,2,3,4,5,6
/8,10,12,13
/20,24,26,40
/48,52,96,104
CLKB
MUX
CLKC
CLKD
SPLL
(8 BIT)
SHUTDOWN/
OE
CONFIG
EPROM
Cypress Semiconductor Corporation
Document #: 38-07449 Rev. *C
3901 North First Street
San Jose
,
CA 95134
408-943-2600
Revised Sept. 07, 2005