CY22381FC Datasheet Download

Part No.:
CY22381FC
Download:
Download Datasheet
Description:
[Three-PLL General Purpose FLASH Programmable Clock Generator]
File Size:
346 K
Page:
9 Pages
Logo:
Manufacturer:
CYPRESS [ CYPRESS SEMICONDUCTOR ]
PCB Prototype
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CY22381
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply Voltage................................................–0.5V to +7.0V
DC Input Voltage ..............................–0.5V to + (V
DD
+ 0.5V)
Storage Temperature .................................. –65°C to +125°C
Junction Temperature .................................................. 125°C
Data Retention at Tj = 125°C ................................> 10 years
Maximum Programming Cycles........................................100
Package Power Dissipation...................................... 250 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) ...........................
2000V
Latch up (per JEDEC 17) ....................................
±200 mA
Operating Conditions
Parameter
V
DD
T
A
Supply Voltage
Commercial Operating Temperature, Ambient
Industrial Operating Temperature, Ambient
C
LOAD_OUT
Max. Load Capacitance
f
REF
External Reference Crystal
External Reference Clock
, Commercial
External Reference Clock
, Industrial
t
PU
Power up time for all VDD's to reach minimum specified voltage (power
ramps must be monotonic)
Description
Min
3.135
0
–40
8
1
1
0.05
Typ
3.3
Max
3.465
+70
+85
15
30
166
150
500
Unit
V
°C
°C
pF
MHz
MHz
MHz
ms
Electrical Characteristics
Parameter
I
OH
I
OL
C
XTAL_MIN
C
XTAL_MAX
C
IN
V
IH
V
IL
I
IH
I
IL
I
OZ
I
DD
I
DDS
Description
Output High Current
Output Low Current
Crystal Load Capacitance
Crystal Load Capacitance
Input Pin Capacitance
HIGH-level Input Voltage
LOW-level Input Voltage
Input HIGH Current
Input LOW Current
Output Leakage Current
Total Power Supply Current
Conditions
V
OH
= V
DD
– 0.5, V
DD
= 3.3 V
V
OL
= 0.5V, V
DD
= 3.3 V
Capload at minimum setting
Capload at maximum setting
Except crystal pins
CMOS levels,% of V
DD
CMOS levels,% of V
DD
V
IN
= V
DD
– 0.3 V
V
IN
= +0.3 V
Three-state outputs
3.3 V Power Supply; 3 outputs at 50 MHz
3.3 V Power Supply; 3 outputs at 166 MHz
Total Power Supply Current in Shutdown active
Shutdown Mode
Min
12
12
70%
Typ
24
24
6
30
7
<1
<1
35
70
5
Max
30%
10
10
10
20
Unit
mA
mA
pF
pF
pF
V
DD
V
DD
μA
μA
μA
mA
mA
μA
Notes
1. Unless otherwise noted, Electrical and Switching Characteristics are guaranteed across these operating conditions.
2. External input reference clock must have a duty cycle between 40% and 60%, measured at V
DD
/2.
3. Guaranteed by design, not 100% tested.
Document #: 38-07012 Rev. *E
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